Field of the Invention
This invention relates to semiconductor chip package design for high speed SerDes signals which achieves low insertion loss, low return loss, and low substrate differential impedance discontinuity between BGA balls and C4 bumps. It also provides an optimization method for calculating parameters of such a package.
Description of the Related Art and Background
To meet the ever increased challenge for high speed chip-to-chip communication, today's semiconductor chips often use high speed SerDes (Serializer/Deserializer) interconnection technology. The cutting edge SerDes data rate has increased from 10 Gb/s to 25-28 Gb/s. SerDes differential impedance discontinuity of a flip-chip package is a key gauge in determining SerDes eye diagram quality. A high package impedance discontinuity from ball grid array (BGA) ball to C4 bump will lead to large signal reflections, increased differential return loss, and degraded signal quality and as a result, reduced eye height and eye width. Unfortunately, in a semiconductor package the impedance mismatch is considered natural because of different substrate structures: BGA ball, via, PTH (plated-through-hole), trace, and C4 bump. They are required to deliver electrical interconnection in a robust mechanical enclosure. Usually each substrate structure has different electrical characteristic impedance. Having them Connected together naturally brings impedance mismatch. If the differential impedance mismatch of a SerDes signal could be lowered, the receiver eye diagram could be opened up wider especially along the voltage axis. A widely opened eye diagram permits a longer cable to be used in data transmission which is essential in datacenter applications from one machine on a rack to a faraway machine on the same rack or to another machine on a different rack. It will also allow two SerDes chips to be placed further apart. If the transmission channel length is not increased, a good eye diagram helps to reduce the bit error rate in data transmission.
The dramatic increase in substrate impedance discontinuity at 25 Gb/s and beyond has made it hard to meet minimum differential return loss specifications from various organizations and has become a major issue in SerDes signal transmission. At 10 Gb/s data rate, the rise time is about 20 ps. It is easy to make the package substrate differential impedance to be within ±10% of its desired value. One widely used approach is to increase the antipad diameter for BGA ball pad, via pad, and PTH pad. An antipad is the clear area around a feature or a landing pad where the metal plane, mostly ground, is removed. Nevertheless, at 25 Gb/s data rate and beyond, these simple approaches are no longer effective in achieving the desired values of less than ±10% differential impedance variation from BGA ball to C4 bump.
FIG. 1 is a substrate cross section for a flip-chip BGA package. SerDes signals from silicon die bumps (C4 bumps) 11 are transmitted to BGA balls 20 through differential traces 13, front-side vias 14, PTHs 16, and back-side vias 18. For a good package design that meets the differential impedance discontinuity requirement of less than ±10% at 10 Gb/s data rate, the impedance variation for the same package design could be close to ±35% when the data rate is increased to 25 Gb/s. Here the fast edge rate of signal switching caused by reduced rise time enlarged signal impedance discontinuity in a package.
FIG. 14 is a substrate cross section for another flip-chip BGA package, which is similar to that shown in FIG. 1 but uses microstrip lines routed on top and bottom metal layers.
Package horizontal interconnection for a SerDes differential signal is realized by routing two traces in parallel in a metal layer. It is widely known that by properly selecting the trace width and spacing of the two traces, it is easy to get desired differential trace impedance of about 100 Ohms. Notwithstanding, for a vertical interconnection, maintaining a 100-Ohm differential impedance from BGA ball to C4 bump (including vias and PTHs) is challenging because the diameters, heights and spacing of these structures are vastly different from each other. This makes their differential impedance different too.
FIG. 2 is a TDR (Time Domain Reflectometry) plot showing a SerDes signal differential impedance discontinuity inside a package and enlargement due to reduced rise time. Different package structures, BGA ball, via, PTH, trace and C4 bump, have different impedances. The TDR plot shows the substrate impedance discontinuity from BGA ball to via/PTH and then from trace to C4 bump. At 10 Gb/s data rate (dash-dotted line), the rise time is about 20 ps and the differential impedance mismatch can be controlled within 10%. However, for the same design at 25 Gb/s data rate (solid line), the rise time is about 8 ps and the differential impedance mismatch could be close to 30% and range from 70 Ohms to 130 Ohms. In other words, the impedance mismatch increases with the increase of data rate.
FIG. 15 are two TDR (Time Domain Reflectometry) plots showing a similar phenomenon.
Because of the high impedance discontinuity and the large signal reflection as well as the big differences in structure, vertical differential impedance optimization to lower its variation becomes challenging. Furthermore, each vertical interconnection, BGA ball, via, and PTH has a slightly bigger landing pad (landing pads are shown in FIG. 1 as bump landing pad 12, via landing pad 15, PTH landing pad 17, and ball landing pad 19). It is the requirement of substrate fabrication to consider the tolerance of the machine alignment with respect to a particular position. These tolerances avoid the opening of an interconnection. However, the various landing pads from layer to layer make the impedance even worse and more difficult to manage. In addition, there are horizontal metal planes from each layer surrounding the vertical interconnections. Their impact on the differential impedance of a vertical interconnection cannot be neglected. Finally, the transition from vertical interconnection to horizontal interconnection imposes a challenge to package designer because matching the impedance at the transition point is difficult.